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  • Writer's pictureConnor Humiston

Creating a Mini-CPU

Updated: Sep 21, 2020

Average computers today are capable of executing billions of operations every second. The speed with which these processes are completed is becoming more and more important with society’s ever-expanding need for quick computation. Thus, it is important to first analyze how these operations work at a primitive level in search of faster procedures before materializing at a larger scale.

The purpose of this project was to create a miniature central processing unit (CPU) that can perform basic arithmetic, comparison, and logical operations. The processes were implemented on the Intel MAX 10 Field Programmable Gate Array (FPGA) utilizing Verilog Hardware Description Language (VHDL) and Quartus Prime. The switches, LEDs, and seven segment displays found on the Terasic DE10-LITE board were used to test each operation programmed in Verilog. The Verilog modules are summarized in the block diagram that follows.

The board layout and component assignments are exhibited below.

The DE10-lite board labelled with seven-segment displays, switches, LEDs, and button keys

Essentially, the two button keys are utilized to change what mode the CPU should be running (computing arithmetic, bitwise comparison, or logical operations). Next, operation selection is determined by switch 8 and 9. The other switches can be switched on or off to represent binary numbers with the least significant bit on the left. Outputs of the binary number operations are then displayed in hexadecimal on the seven-segment displays. Furthermore, if a carry or remainder is produced, LED 8 and 9 will illuminate respectively. Mode and operation selection truth tables are illustrated here:

Multiplexed selection between modes

Multiplexer selection of operation in specific modes



Hexadecimal equivalents for recognizable output digits


This module takes in binary inputs and outputs hexadecimal numbers to the seven-segment display. Hexadecimal digits can be created by turning on individual LEDs from the display, as pictured above with individual LEDs labeled with different letters.

The SevenSegment module uses binary values (following the pattern gfedcba) from the table on the right that correspond to the correct hexadecimal representation on the display. It is important to note that the LEDs for the seven segment displays on the MAX10 board are actually on for low inputs and off when the input is high so the Verilog code actually represents values opposite to those in the table.


Addition (𝑥 + 𝑦), subtraction (𝑥 - 𝑦), multiplication-by-2 (2 × 𝑧), and division-by-2 (2 ÷ 𝑧) operations can be completed with the Arithmetic module. A ripple carry adder (implemented with full adders) and full subtractor were coded for addition and subtraction operations. Multiplication and division by two were easy to carry out in binary with a simple shift left or right due to binary's base-two foundation.


The logical module simply includes bitwise AND, OR, XOR, and NOT operations. In other words, depending on the chosen process, binary from input numbers x, y, and z represented by switches 0 through 7 (as described in the above) will be manipulated bit by bit.


The comparison mode includes equal-to, greater-than, less-than, and maximum operations. See test results of this module and the others in the results section below.


This module takes on the role of a two-to-four multiplexer, meaning two select bits (that can represent four numbers numbers 0-3) are used to chose between four inputs. The multiplexer was utilized in other modules to select between inputs such as which module should be output to the seven segment display.


Last but not least, the top module takes in the buttons and switches as inputs, and utilizes the Arithmetic, Logical, Comparison, Multiplexer, and SevenSegment modules to create outputs for the ten LEDs and two seven-segment displays. The other modules are instantiated and the mode is selected in the top module. To select between modes, Project1_Top exploits conditional statements that change a register value on the positive edge of a button press. The negative edge would have been ideal since the button keys are high by default, but board defects/debouncer issues resulted in the contrary. KEY0 switches between Arithmetic and the other two modules. KEY1 switches between the Comparison and Logic modules. Once a mode is selected, hexadecimal outputs will appear on the seven segment displays and binary outputs will appear on the LEDs.



The purpose of this project was to create a miniature CPU that can perform basic arithmetic, comparison, and logical operations on the MAX 10 FPGA Verilog and Quartus Prime. Though difficult at first to visualize how each individual logical component or Verilog expression fits in with each other, each operation fell into its right place in the end. The CPU could be improved in the future by implementing a more intuitive way of switching modes with, for instance, a reset button and an incremental way to navigate the different modes. All in all, it was fascinating to take digital logic ideology and apply it to a small-scale version of something many of us use every day without thinking twice about the detailed work that went into designing it.

The result of multiplying z = 0xA7 by 2 with indication of the carry on LEDR8 and the HEX1 decimal point

Check out the entire project write up and the board's outputs in the Electrical and Computer section here or the Verilog code here.


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